 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| QUAD MULTIPLEXER/LATCH FEATURES s s s s s s s s s s Max. propagation delay of 1100ps Max. enable to output delay of 1400ps IEE min. of -80mA Industry standard 100K ECL levels Extended supply voltage option: VEE = -4.2V to -5.5V Voltage and temperature compensation for improved noise immunity Internal 75K input pull-down resistors 50% faster than Fairchild Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages SY100S355 DESCRIPTION The SY100S355 offers four transparent latches with differential outputs and is designed for use in highperformance ECL systems. The Select inputs (S0, S1) select one of the two sources of input data (D0 or D1) to the latch. The Select inputs can also force the outputs to a logic LOW when the latch is in the transparent mode. The latches are in the transparent mode when both Enables (E1, E2) are at a logic LOW state. In the transparent mode, the Select inputs can pass an input logic HIGH from D0 or D1 to the output. If the Select inputs are tied together, then input data from either D0 or D1 is always passed through. A rising edge on either Enable input will latch the outputs with the most recent data at the latch inputs being stored. The Master Reset (MR) input overrides all other inputs and takes the Q outputs to a logic LOW. The inputs on this device have 75K pull-down resistors. BLOCK DIAGRAM S0 S1 D0a D D1a E CD D0b D D1b E CD D0c D D1c E CD D0d Qc Q Qc Qb Q Qb Qa Q Qa PIN CONFIGURATIONS D0b D1a VEES D1b D0a Qa Qa 11 10 9 8 7 6 5 S0 S1 VEE VEES MR E1 E2 12 13 14 15 16 17 18 4 3 2 1 28 27 26 Qb Qb VCCA VCC VCC Qc Qc Top View PLCC J28-1 19 20 21 22 23 24 25 D0c D1c D0d VEES D1d Qd E1 MR VEE Qd E2 S1 D0c D1c D0d D1d Qd Qd 1 2 3 4 5 6 24 23 22 21 20 19 18 Top View Flatpack F24-1 17 16 15 14 S0 D1b D0b D1a D0a Qa Qa 13 7 8 9 10 11 12 Qc VCC VCCA Qc D1d E E1 E2 MR CD Qd Rev.: G Qb Qb Amendment: /0 D Q Qd 1 Issue Date: July, 1999 Micrel SY100S355 PIN NAMES Pin E1 - E2 S0, S1 MR Dna - Dnd Qa - Qd Qa -- Qd VEES VCCA Function Enable Inputs (Active LOW) Select Inputs Master Reset Data Inputs Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs TRUTH TABLE(1) Inputs MR H L L L L L L L L L L E1 X L L L L L L L L H X E2 X L L L L L L L L X H S1 X H H L L L H H H X X S0 X H H L L H L L L X X D1X X H L X X X H X L X X D0X X X X H L X X H L X X Outputs QX H L H L H H L L QX L H L H L L H H H L Latched Latched NOTE: 1. H = High Voltage Level L = Low Voltage Level X = Don't Care DC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND Symbol IIH Parameter Input HIGH Current S0, S1 E1, E2 Dna, Dnd MR Power Supply Current Min. -- -- -- -- -80 Typ. -- -- -- -- -57 Max. 220 350 340 430 -40 mA Inputs Open Unit A Condition VIN = VIH (Max.) IEE 2 Micrel SY100S355 AC ELECTRICAL CHARACTERISTICS CERPACK VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND TA = 0C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Propagation Delay Dna - Dnd to Output (Transparent Mode) Propagation Delay S0, S1 to Output (Transparent Mode) Propagation Delay E1, E2 to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Set-up Time Dna - Dnd S0, S1 MR (Release Time) Hold Time Dna - Dnd S0, S1 Pulse Width LOW, E1, E2 Pulse Width HIGH, MR Min. 300 Max. 1200 TA = +25C Min. 300 Max. 1200 TA = +85C Min. 300 Max. 1200 Unit ps Condition 300 1500 300 1500 300 1500 ps 300 300 300 1500 1200 900 300 300 300 1500 1200 900 300 300 300 1500 1200 900 ps ps ps ps 700 1200 1000 400 400 1000 1000 -- -- -- -- -- -- -- 700 1200 1000 400 400 1000 1000 -- -- -- -- -- -- -- 700 1200 1000 400 400 1000 1000 -- -- -- ps -- -- -- -- ps ps tH tPW (L) tPW (H) PLCC VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND TA = 0C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Propagation Delay Dna - Dnd to Output (Transparent Mode) Propagation Delay S0, S1 to Output (Transparent Mode) Propagation Delay E1, E2 to Output Propagation Delay MR to Output Transition Time 20% to 80%, 80% to 20% Set-up Time Dna - Dnd S0, S1 MR (Release Time) Hold Time Dna - Dnd S0, S1 Pulse Width LOW, E1, E2 Pulse Width HIGH, MR Min. 300 Max. 1100 TA = +25C Min. 300 Max. 1100 TA = +85C Min. 300 Max. 1100 Unit ps Condition 300 1400 300 1400 300 1400 ps 300 300 300 1400 1100 900 300 300 300 1400 1100 900 300 300 300 1400 1100 900 ps ps ps ps 700 1200 1000 300 300 1000 1000 -- -- -- -- -- -- -- 3 700 1200 1000 300 300 1000 1000 -- -- -- -- -- -- -- 700 1200 1000 300 300 1000 1000 -- -- -- ps -- -- -- -- ps ps tH tPW (L) tPW (H) Micrel SY100S355 TIMING DIAGRAMS 0.7 0.1 ns -0.95V Dna - Dnd S0, S1 -1.69V tpw -0.95V ENABLE TRANSPARENT tPHL, tPLH LATCHED tPHL, tPLH TRANSPARENT -1.69V tPHL, tPLH 80% 50% 20% tTHL, tTLH OUTPUT Enable Timing RESET TIMING DATA ENABLE TRANSPARENT LATCHED TRANSPARENT tR RELEASE TIME RESET/SET tPHL, tPLH tpw tPHL, tPLH tPHL, tPLH OUTPUT Reset Timing 4 Micrel SY100S355 TIMING DIAGRAMS -0.95V S0, S1 tS tH 50% -1.69V -0.95V DATA tS tH 50% -1.69 -0.95V E1, E2 50% -1.69V Data Set-up and Hold Times NOTES: 1. VEE = -4.2V to -5.5V unless otherwise specified; VCC = VCCA = GND 2. ts is the minimum time before the transition of the clock that information must be present at the data input. 3. tH is the minimum time after the transition of the clock that information must remain unchanged at the data input. PRODUCT ORDERING CODE Ordering Code SY100S355FC SY100S355JC SY100S355JCTR Package Type F24-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial 5 Micrel SY100S355 24 LEAD CERPACK (F24-1) Rev. 03 6 Micrel SY100S355 28 LEAD PLCC (J28-1) Rev. 03 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 7 |
Price & Availability of SY100S355JC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |